The Pentium-M CPU doesn't, and never has (and given the advent of the dual-core units, likely never will) support hyperthreading.

The 9400 is a decent desktop replacement system - it's as good as any true mobile out there. That is, there are still companies selling desktop CPUs in notebook chassis - if you want one of those, along with the negatives that come with them (excess heat, short battery life, bulk, short component life), there are other options.

The Pentium-M, from ALL manufacturers, locks out hyperthreading. Dual-core is far superior anyway.

Great in theory, but useless. As I posted earlier, the Pentium-M doesn't and never has supported hyperthreading, so having such an option would be useless.

Hello ejn63, how are ya doing this fine day? Very well, I hope. First thank you for your post, it is very informative. I should have been clearer in my post to note that I was referring to Intel Core Duo processors, (previously code name Yonah) which is the replacement for the Pentium M chips. According to Intel's literature, this is a brand new chip. Really, a Pentium M with two cores maybe. Anyway, this (new) chip can use either the Intel 945, 945PM, 955X, and the 975X chipsets. Only the 945's do not support HT Technology. I had hope Dell would have used 955X chipset in its Inspiring 9400 model and enable both duo core and HT. This would have been a real screamer and a true desktop replacement. What do you think?

The 955X is a Pentium 4 chipset. The Pentium-M requires its own chipset and won't work with it.

Thanks ejn63, i thought 955x was mobil chipset.

 

Inspiron 8200 with Dell Bios A11
Intel Pentium 4 – M 2.4 Ghz
512MB, DDR, 266M (2 DIMM)
64 MB DDR 4xAGP ATI Mobility Radeon 9000
40 GB Hard Drive 5400 rpm
15” UXGA 1600x1200 Ultra Sharp Display
Crystal WDM Audio Codec
Samaung CDRW/DVD SN-324B
Microsoft Windows XP Pro.
Microsoft Office 2002 Small business

Hyperthreading is a dead issue and will eventually disappear in favor of true dual-core CPUs. It was a stopgap measure intended to make a single CPU work like two - now that a single die can have two (or more) cores, its day is over.

I'm sure dell will pull an XPS soon that supports hyperthreading. Remember, they're trying to sell luxury like ferrari's nowadays.

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@DogDriver1 wrote:

Hi ejn63 and sblive, ejn63 your point of view is very interesting. I was not aware that dual-core would eclipse hyper-threading. Currently, Intel's web pages on duo-core technology list both HT and Duo-Core hand in hand as if they were about to get married.

Inspiron 8200 with Dell Bios A10
Intel Pentium 4 – M 2.4 Ghz
512MB, DDR, 266M (2 DIMM)
64 MB DDR 4xAGP ATI Mobility Radeon 9000
40 GB Hard Drive 5400 rpm
15” UXGA 1600x1200 Ultra Sharp Display
Crystal WDM Audio Codec
Samaung CDRW/DVD SN-324B
Microsoft Windows XP Pro.
Microsoft Office 2002 Small business

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Dual core Pentium 4s might still get a benefit from HyperThreading, giving an effective logical 4 cores.

That said, HyperThreading was a band-aid around design issues with the Pentium 4 processor that the Pentium M, and all AMD chipsets do not have. HT actually hurt performance in many cases, and it is guaranteed that it would hurt performance in nearly all cases on Pentium M CPUs. (Note, the Core Duo is based on the same architecture as the Pentium M.)

Basically, back when the Pentium 4 was conceived, Intel designed the Pentium 4 in such a way that it could scale to extremely high clock speeds, but did not perform nearly as well in terms of instructions per clock cycle as its predecessor, the Pentium 3. Intel was banking on being able to ramp up clock speeds high enough to counteract this IPC deficiency, but in the end they weren't able to pull it off - Processors with lower clock speed but higher IPC (such as the Athlon XP and later the Athlon 64) continued to maintain the performance crown in the majority of applications.

Technical explanation follows:

The main design difference was in pipelining - Almost all modern CPUs will actually take a number of clock cycles to complete an instruction, but they can have multiple instructions in their pipeline. The less work that is done in a given stage of a pipeline, the faster the clock speed for that stage can be. To allow the incredibly high clock speed of the P-4, Intel designed it with an incredibly long pipeline. The problem with a long pipeline is that if one instruction depends on the result of a previous instruction, it has to wait for that instruction to complete. In some cases, such as deciding whether to branch (if this then do that, else do something else), the CPU could make an educated guess as to whether to branch, and then start executing it to avoid having the pipeline stall. When the instruction it was waiting for a result for finished, it would decide whether it had guessed correctly. If it did, it would continue. If it didn't, it would have to go back to where the branch occurred and everything it had done while waiting would be wasted. Needless to say, instruction scheduling becomes more and more difficult as the pipeline length increases, and the penalty for a branch misprediction increases too. That's why while AMD Athlons couldn't reach the high raw clock speeds that P-4s could, they could keep up in real world performance with a P-4 running at over 1.5 times the clock speed - the Athlons weren't being crippled by a deep pipeline. (Note, this also holds true for the Pentium III and its direct descendent, the Pentium M. Yes, the P-M is based on the P-III.)

HyperThreading made the job of the P-4's instruction scheduler easier, and reduced the penalty of branch mispredictions. Previously, the instruction scheduler had to resolve dependencies of 20 instructions from whatever thread was running at the time, and could pay up to 20 instructions worth of branch misprediction penalty. With HyperThreading in an ideal situation, two threads would share the pipeline. As a result, only 10 instructions from each thread had to be guaranteed to be conflict-free, and a branch misprediction would at worst case throw out 10 instructions from one thread. (This is in a situation where each thread was using equal portions of CPU power.) The shorter a CPU's pipeline is, the less benefit such an approach provides.